Enhancing a Reconfigurable Instruction Set Processor with Partial Predication and Virtual Opcode Support
نویسندگان
چکیده
A previously proposed Reconfigurable Instruction Set Processor (RISP) architecture, which tightly couples a coarse-grain Reconfigurable Functional Unit (RFU) to a RISC processor, is considered. Two architectural enhancements, namely partial predicated execution and virtual opcode are presented. An automated development framework for the introduced architecture is proposed. In order to evaluate both the architecture and the development framework a complete MPEG-2 encoder application is used. The efficiency of the predicated execution is proved and impressive speedup of the application is produced. Also, the use of virtual opcode to alleviate the opcode space explosion is demonstrated.
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